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[/] [cpu6502_true_cycle/] [trunk/] - Rev 14

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14 More optimizations...
- Second Phaze of removing unused nets & registers
- Added Verilog source on demand by some customers (for trial use)		 fpga_is_funny 5638d 14h /cpu6502_true_cycle/trunk/
13 DELETED directory cpu6502_true_cycle/doc/HTML - use the HTML.RAR file instead fpga_is_funny 5643d 11h /cpu6502_true_cycle/trunk/
12 no message fpga_is_funny 5643d 11h /cpu6502_true_cycle/trunk/
11 *** EMERGENCY BUGFIX ***
- Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
- OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads
from $02FF and $0200, instead of $02FF and $0300)		 fpga_is_funny 5643d 12h /cpu6502_true_cycle/trunk/
9 This commit was generated by cvs2svn to compensate for changes in r8, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5643d 13h /cpu6502_true_cycle/trunk/
7 This commit was generated by cvs2svn to compensate for changes in r6, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5643d 13h /cpu6502_true_cycle/trunk/
5 Bugfixes for all relationchips with interrupts BRK, IRQ and NMI.
The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down.
The "B" status flag was never set within BRK.
The relationchip between addresses and data while writing onto the stack was badly misalligned.		 fpga_is_funny 5905d 16h /cpu6502_true_cycle/trunk/
4 Corrected HTML files for documentation (change $log$ to $Log$ in all VHDL files in first release) fpga_is_funny 5914d 14h /cpu6502_true_cycle/trunk/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5914d 15h /cpu6502_true_cycle/trunk/
1 Standard project directories initialized by cvs2svn. 5914d 15h /cpu6502_true_cycle/trunk/

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