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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] - Rev 18

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Rev Log message Author Age Path
18 New directory structure. root 5562d 18h /cpu6502_true_cycle/trunk/rtl/
15 CORRECTED "RTI" (wrong: use of stack pointer)
RENAME all states of "FSM Execution Unit" for better reading
(90%) Finish working for Specification of cpu6502_tc		 fpga_is_funny 5574d 20h /trunk/rtl/
14 More optimizations...
- Second Phaze of removing unused nets & registers
- Added Verilog source on demand by some customers (for trial use)		 fpga_is_funny 5621d 17h /trunk/rtl/
12 no message fpga_is_funny 5626d 14h /trunk/rtl/
11 *** EMERGENCY BUGFIX ***
- Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
- OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads
from $02FF and $0200, instead of $02FF and $0300)		 fpga_is_funny 5626d 16h /trunk/rtl/
9 This commit was generated by cvs2svn to compensate for changes in r8, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5626d 16h /trunk/rtl/
7 This commit was generated by cvs2svn to compensate for changes in r6, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5626d 17h /trunk/rtl/
5 Bugfixes for all relationchips with interrupts BRK, IRQ and NMI.
The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down.
The "B" status flag was never set within BRK.
The relationchip between addresses and data while writing onto the stack was badly misalligned.		 fpga_is_funny 5888d 20h /trunk/rtl/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5897d 18h /trunk/rtl/

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