OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] [cpu_lecture/] [trunk/] [src/] - Rev 21

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
21 fixed bug in Sign bit computation for SUB and CP instructions jsauermann 5240d 22h /cpu_lecture/trunk/src/
20 readability of 95xx instructions improved jsauermann 5272d 19h /cpu_lecture/trunk/src/
19 another bug in the decoding of two-cycle instructions fixed jsauermann 5272d 19h /cpu_lecture/trunk/src/
18 fixed a bug that caused double execution of some 95xx instructions jsauermann 5275d 21h /cpu_lecture/trunk/src/
17 fixed missing carry flag for ROR instruction jsauermann 5279d 19h /cpu_lecture/trunk/src/
16 fixed missing RD_M signal for IN instruction jsauermann 5288d 21h /cpu_lecture/trunk/src/
15 fixed SP auto inc/dec problem jsauermann 5288d 23h /cpu_lecture/trunk/src/
14 fixed wrong Q_RSEL for LDD instruction jsauermann 5290d 19h /cpu_lecture/trunk/src/
13 fixed fault in LDD/STD decoding jsauermann 5291d 19h /cpu_lecture/trunk/src/
12 fixed bug in decoding of I/O address for SP jsauermann 5292d 19h /cpu_lecture/trunk/src/
11 fixed fault is BSET/BCLR instruction jsauermann 5294d 19h /cpu_lecture/trunk/src/
10 wait decoder fault fixed jsauermann 5295d 01h /cpu_lecture/trunk/src/
6 support multiple port sizes in make_mem jsauermann 5296d 03h /cpu_lecture/trunk/src/
2 initial check-in jsauermann 5300d 21h /cpu_lecture/trunk/src/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.