URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

[/] [csa/] [trunk/] - Rev 38

Rev	Log message	Author	Age	Path
38	improve the ledseg control module the register h must be 2bits width	simon111	5525d 23h	/csa/trunk/
37	improve write_data systemcall,	simon111	5526d 05h	/csa/trunk/
36	improve read_date vpi sytemcall, add offset and size argument	simon111	5526d 06h	/csa/trunk/
35	csa cli support binary test data	simon111	5526d 11h	/csa/trunk/
34	add binary test date (only sw_sim now )	simon111	5526d 13h	/csa/trunk/
33	improve ledseg controler module	simon111	5527d 01h	/csa/trunk/
32	fix a compile error	simon111	5527d 01h	/csa/trunk/
31	remove pc execute file	simon111	5527d 01h	/csa/trunk/
30	begin vailating on fpga	simon111	5527d 01h	/csa/trunk/
29	fix some bugs	simon111	5528d 01h	/csa/trunk/
28	create a quartus10 project for test the core	simon111	5528d 01h	/csa/trunk/
27	improve makefiles	simon111	5528d 12h	/csa/trunk/
24	New directory structure.	root	5564d 18h	/csa/trunk/
23	testing key_schedule module	simon111	5648d 01h	/trunk/
22	decrypt module testbench update	simon111	5688d 01h	/trunk/
21	decrypt module passed basicly, it's not good code type	simon111	5688d 01h	/trunk/
20	finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why	simon111	5702d 00h	/trunk/
19	add a modelsim project to samulate the stream_cypher module	simon111	5702d 00h	/trunk/
18	try to add decrypt module (not finished yet)	simon111	5712d 01h	/trunk/
17	finish block_decypher module	simon111	5763d 07h	/trunk/