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[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 129

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Rev Log message Author Age Path
129 New documentation. mohor 7466d 16h /dbg_interface/tags/asyst_2/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7469d 00h /dbg_interface/tags/asyst_2/
126 run_sim.scr renamed to run_sim for VATS. mohor 7472d 00h /dbg_interface/tags/asyst_2/
124 Display for VATS added. mohor 7473d 21h /dbg_interface/tags/asyst_2/
123 All flipflops are reset. mohor 7473d 21h /dbg_interface/tags/asyst_2/
121 Port signals are all set to zero after reset. mohor 7476d 21h /dbg_interface/tags/asyst_2/
120 test stall_test added. mohor 7477d 00h /dbg_interface/tags/asyst_2/
119 cpu_stall_o activated as soon as bp occurs. mohor 7477d 00h /dbg_interface/tags/asyst_2/
117 Define name changed. mohor 7478d 20h /dbg_interface/tags/asyst_2/
116 Data latching changed when testing WB. mohor 7478d 21h /dbg_interface/tags/asyst_2/
115 More debug data added. mohor 7479d 00h /dbg_interface/tags/asyst_2/
114 CRC generation iand verification in bench changed. mohor 7479d 02h /dbg_interface/tags/asyst_2/
113 IDCODE test improved. mohor 7479d 03h /dbg_interface/tags/asyst_2/
112 dbg_tb_defines.v not used. mohor 7479d 21h /dbg_interface/tags/asyst_2/
111 Define tap_defines.v added to test bench. mohor 7479d 21h /dbg_interface/tags/asyst_2/
110 Waiting for "ready" improved. mohor 7479d 22h /dbg_interface/tags/asyst_2/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7480d 03h /dbg_interface/tags/asyst_2/
106 Sensitivity list updated. simons 7481d 01h /dbg_interface/tags/asyst_2/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7481d 16h /dbg_interface/tags/asyst_2/
102 New version. mohor 7481d 17h /dbg_interface/tags/asyst_2/

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