URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 139

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Rev	Log message	Author	Age	Path
139	New release of the debug interface (3rd. release).	igorm	7388d 07h	/dbg_interface/tags/asyst_2/rtl/
138	Temp version before changing dbg interface.	igorm	7394d 11h	/dbg_interface/tags/asyst_2/rtl/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7446d 17h	/dbg_interface/tags/asyst_2/rtl/
123	All flipflops are reset.	mohor	7451d 14h	/dbg_interface/tags/asyst_2/rtl/
121	Port signals are all set to zero after reset.	mohor	7454d 14h	/dbg_interface/tags/asyst_2/rtl/
119	cpu_stall_o activated as soon as bp occurs.	mohor	7454d 18h	/dbg_interface/tags/asyst_2/rtl/
117	Define name changed.	mohor	7456d 13h	/dbg_interface/tags/asyst_2/rtl/
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7457d 20h	/dbg_interface/tags/asyst_2/rtl/
106	Sensitivity list updated.	simons	7458d 18h	/dbg_interface/tags/asyst_2/rtl/
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7459d 09h	/dbg_interface/tags/asyst_2/rtl/
102	New version.	mohor	7459d 10h	/dbg_interface/tags/asyst_2/rtl/
101	Almost finished.	mohor	7459d 11h	/dbg_interface/tags/asyst_2/rtl/
100	* empty log message *	mohor	7460d 13h	/dbg_interface/tags/asyst_2/rtl/
99	cpu registers added.	mohor	7460d 13h	/dbg_interface/tags/asyst_2/rtl/
97	Working.	mohor	7461d 16h	/dbg_interface/tags/asyst_2/rtl/
95	Temp version.	mohor	7462d 05h	/dbg_interface/tags/asyst_2/rtl/
94	temp version. Resets will be changed in next version.	mohor	7462d 15h	/dbg_interface/tags/asyst_2/rtl/
93	tmp version.	mohor	7463d 16h	/dbg_interface/tags/asyst_2/rtl/
92	temp version.	mohor	7466d 20h	/dbg_interface/tags/asyst_2/rtl/
91	tmp version.	mohor	7467d 15h	/dbg_interface/tags/asyst_2/rtl/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 139

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