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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 147

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Rev Log message Author Age Path
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7380d 12h /dbg_interface/tags/asyst_2/rtl/
146 Changes for the FormalPRO. igorm 7384d 09h /dbg_interface/tags/asyst_2/rtl/
144 Port names and defines for the supported CPUs changed. igorm 7384d 14h /dbg_interface/tags/asyst_2/rtl/
143 Signals for easier debugging removed. igorm 7384d 16h /dbg_interface/tags/asyst_2/rtl/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7385d 11h /dbg_interface/tags/asyst_2/rtl/
139 New release of the debug interface (3rd. release). igorm 7388d 05h /dbg_interface/tags/asyst_2/rtl/
138 Temp version before changing dbg interface. igorm 7394d 09h /dbg_interface/tags/asyst_2/rtl/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7446d 16h /dbg_interface/tags/asyst_2/rtl/
123 All flipflops are reset. mohor 7451d 12h /dbg_interface/tags/asyst_2/rtl/
121 Port signals are all set to zero after reset. mohor 7454d 12h /dbg_interface/tags/asyst_2/rtl/
119 cpu_stall_o activated as soon as bp occurs. mohor 7454d 16h /dbg_interface/tags/asyst_2/rtl/
117 Define name changed. mohor 7456d 12h /dbg_interface/tags/asyst_2/rtl/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7457d 18h /dbg_interface/tags/asyst_2/rtl/
106 Sensitivity list updated. simons 7458d 17h /dbg_interface/tags/asyst_2/rtl/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7459d 07h /dbg_interface/tags/asyst_2/rtl/
102 New version. mohor 7459d 08h /dbg_interface/tags/asyst_2/rtl/
101 Almost finished. mohor 7459d 09h /dbg_interface/tags/asyst_2/rtl/
100 *** empty log message *** mohor 7460d 11h /dbg_interface/tags/asyst_2/rtl/
99 cpu registers added. mohor 7460d 11h /dbg_interface/tags/asyst_2/rtl/
97 Working. mohor 7461d 14h /dbg_interface/tags/asyst_2/rtl/

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