OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 82

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
82 New directory structure. New version of the debug interface. mohor 7500d 15h /dbg_interface/tags/asyst_2/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7500d 15h /dbg_interface/tags/asyst_2/rtl/
77 MBIST chain connection fixed. mohor 7561d 12h /dbg_interface/tags/asyst_2/rtl/
73 CRC logic changed. mohor 7561d 13h /dbg_interface/tags/asyst_2/rtl/
71 Mbist support added. simons 7563d 20h /dbg_interface/tags/asyst_2/rtl/
67 Lower two address lines must be always zero. simons 7596d 16h /dbg_interface/tags/asyst_2/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7597d 15h /dbg_interface/tags/asyst_2/rtl/
63 Three more chains added for cpu debug access. simons 7617d 16h /dbg_interface/tags/asyst_2/rtl/
61 Lapsus fixed. simons 7645d 16h /dbg_interface/tags/asyst_2/rtl/
59 Reset value for riscsel register set to 1. simons 7645d 16h /dbg_interface/tags/asyst_2/rtl/
57 Multiple cpu support added. simons 7645d 17h /dbg_interface/tags/asyst_2/rtl/
53 Trst active high. Inverted on higher layer. mohor 7912d 15h /dbg_interface/tags/asyst_2/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7912d 15h /dbg_interface/tags/asyst_2/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7940d 03h /dbg_interface/tags/asyst_2/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8095d 15h /dbg_interface/tags/asyst_2/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8103d 21h /dbg_interface/tags/asyst_2/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8110d 17h /dbg_interface/tags/asyst_2/rtl/
44 Signal names changed to lower case. mohor 8110d 17h /dbg_interface/tags/asyst_2/rtl/
43 Intentional error removed. mohor 8115d 16h /dbg_interface/tags/asyst_2/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8115d 18h /dbg_interface/tags/asyst_2/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.