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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 94

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Rev Log message Author Age Path
94 temp version. Resets will be changed in next version. mohor 7499d 05h /dbg_interface/tags/asyst_2/rtl/
93 tmp version. mohor 7500d 06h /dbg_interface/tags/asyst_2/rtl/
92 temp version. mohor 7503d 10h /dbg_interface/tags/asyst_2/rtl/
91 tmp version. mohor 7504d 05h /dbg_interface/tags/asyst_2/rtl/
90 tmp version. mohor 7505d 00h /dbg_interface/tags/asyst_2/rtl/
89 temp4 version. mohor 7506d 05h /dbg_interface/tags/asyst_2/rtl/
88 temp3 version. mohor 7507d 00h /dbg_interface/tags/asyst_2/rtl/
87 tmp2 version. mohor 7508d 05h /dbg_interface/tags/asyst_2/rtl/
86 Tmp version. mohor 7521d 01h /dbg_interface/tags/asyst_2/rtl/
83 Small fix. mohor 7521d 02h /dbg_interface/tags/asyst_2/rtl/
82 New directory structure. New version of the debug interface. mohor 7521d 02h /dbg_interface/tags/asyst_2/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7521d 02h /dbg_interface/tags/asyst_2/rtl/
77 MBIST chain connection fixed. mohor 7581d 23h /dbg_interface/tags/asyst_2/rtl/
73 CRC logic changed. mohor 7582d 01h /dbg_interface/tags/asyst_2/rtl/
71 Mbist support added. simons 7584d 08h /dbg_interface/tags/asyst_2/rtl/
67 Lower two address lines must be always zero. simons 7617d 03h /dbg_interface/tags/asyst_2/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7618d 03h /dbg_interface/tags/asyst_2/rtl/
63 Three more chains added for cpu debug access. simons 7638d 04h /dbg_interface/tags/asyst_2/rtl/
61 Lapsus fixed. simons 7666d 03h /dbg_interface/tags/asyst_2/rtl/
59 Reset value for riscsel register set to 1. simons 7666d 04h /dbg_interface/tags/asyst_2/rtl/

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