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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 146

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Rev Log message Author Age Path
146 Changes for the FormalPRO. igorm 7453d 03h /dbg_interface/tags/asyst_2/rtl/verilog/
144 Port names and defines for the supported CPUs changed. igorm 7453d 09h /dbg_interface/tags/asyst_2/rtl/verilog/
143 Signals for easier debugging removed. igorm 7453d 10h /dbg_interface/tags/asyst_2/rtl/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7454d 06h /dbg_interface/tags/asyst_2/rtl/verilog/
139 New release of the debug interface (3rd. release). igorm 7457d 00h /dbg_interface/tags/asyst_2/rtl/verilog/
138 Temp version before changing dbg interface. igorm 7463d 04h /dbg_interface/tags/asyst_2/rtl/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7515d 10h /dbg_interface/tags/asyst_2/rtl/verilog/
123 All flipflops are reset. mohor 7520d 06h /dbg_interface/tags/asyst_2/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7523d 07h /dbg_interface/tags/asyst_2/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7523d 10h /dbg_interface/tags/asyst_2/rtl/verilog/
117 Define name changed. mohor 7525d 06h /dbg_interface/tags/asyst_2/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7526d 13h /dbg_interface/tags/asyst_2/rtl/verilog/
106 Sensitivity list updated. simons 7527d 11h /dbg_interface/tags/asyst_2/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7528d 02h /dbg_interface/tags/asyst_2/rtl/verilog/
102 New version. mohor 7528d 03h /dbg_interface/tags/asyst_2/rtl/verilog/
101 Almost finished. mohor 7528d 04h /dbg_interface/tags/asyst_2/rtl/verilog/
100 *** empty log message *** mohor 7529d 06h /dbg_interface/tags/asyst_2/rtl/verilog/
99 cpu registers added. mohor 7529d 06h /dbg_interface/tags/asyst_2/rtl/verilog/
97 Working. mohor 7530d 08h /dbg_interface/tags/asyst_2/rtl/verilog/
95 Temp version. mohor 7530d 22h /dbg_interface/tags/asyst_2/rtl/verilog/

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