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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 152

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Rev Log message Author Age Path
152 CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
check-in.		 igorm 7411d 21h /dbg_interface/tags/asyst_2/rtl/verilog/
150 Zero is shifted out when CTRL_READ command is active. igorm 7412d 16h /dbg_interface/tags/asyst_2/rtl/verilog/
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7414d 21h /dbg_interface/tags/asyst_2/rtl/verilog/
146 Changes for the FormalPRO. igorm 7418d 18h /dbg_interface/tags/asyst_2/rtl/verilog/
144 Port names and defines for the supported CPUs changed. igorm 7418d 23h /dbg_interface/tags/asyst_2/rtl/verilog/
143 Signals for easier debugging removed. igorm 7419d 01h /dbg_interface/tags/asyst_2/rtl/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7419d 21h /dbg_interface/tags/asyst_2/rtl/verilog/
139 New release of the debug interface (3rd. release). igorm 7422d 15h /dbg_interface/tags/asyst_2/rtl/verilog/
138 Temp version before changing dbg interface. igorm 7428d 19h /dbg_interface/tags/asyst_2/rtl/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7481d 01h /dbg_interface/tags/asyst_2/rtl/verilog/
123 All flipflops are reset. mohor 7485d 21h /dbg_interface/tags/asyst_2/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7488d 21h /dbg_interface/tags/asyst_2/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7489d 01h /dbg_interface/tags/asyst_2/rtl/verilog/
117 Define name changed. mohor 7490d 21h /dbg_interface/tags/asyst_2/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7492d 04h /dbg_interface/tags/asyst_2/rtl/verilog/
106 Sensitivity list updated. simons 7493d 02h /dbg_interface/tags/asyst_2/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7493d 17h /dbg_interface/tags/asyst_2/rtl/verilog/
102 New version. mohor 7493d 17h /dbg_interface/tags/asyst_2/rtl/verilog/
101 Almost finished. mohor 7493d 18h /dbg_interface/tags/asyst_2/rtl/verilog/
100 *** empty log message *** mohor 7494d 20h /dbg_interface/tags/asyst_2/rtl/verilog/

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