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[/] [dbg_interface/] [tags/] [asyst_3/] - Rev 121

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Rev	Log message	Author	Age	Path
121	Port signals are all set to zero after reset.	mohor	7488d 14h	/dbg_interface/tags/asyst_3/
120	test stall_test added.	mohor	7488d 16h	/dbg_interface/tags/asyst_3/
119	cpu_stall_o activated as soon as bp occurs.	mohor	7488d 17h	/dbg_interface/tags/asyst_3/
117	Define name changed.	mohor	7490d 13h	/dbg_interface/tags/asyst_3/
116	Data latching changed when testing WB.	mohor	7490d 13h	/dbg_interface/tags/asyst_3/
115	More debug data added.	mohor	7490d 17h	/dbg_interface/tags/asyst_3/
114	CRC generation iand verification in bench changed.	mohor	7490d 18h	/dbg_interface/tags/asyst_3/
113	IDCODE test improved.	mohor	7490d 19h	/dbg_interface/tags/asyst_3/
112	dbg_tb_defines.v not used.	mohor	7491d 14h	/dbg_interface/tags/asyst_3/
111	Define tap_defines.v added to test bench.	mohor	7491d 14h	/dbg_interface/tags/asyst_3/
110	Waiting for "ready" improved.	mohor	7491d 15h	/dbg_interface/tags/asyst_3/
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7491d 20h	/dbg_interface/tags/asyst_3/
106	Sensitivity list updated.	simons	7492d 18h	/dbg_interface/tags/asyst_3/
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7493d 09h	/dbg_interface/tags/asyst_3/
102	New version.	mohor	7493d 09h	/dbg_interface/tags/asyst_3/
101	Almost finished.	mohor	7493d 10h	/dbg_interface/tags/asyst_3/
100	* empty log message *	mohor	7494d 13h	/dbg_interface/tags/asyst_3/
99	cpu registers added.	mohor	7494d 13h	/dbg_interface/tags/asyst_3/
97	Working.	mohor	7495d 15h	/dbg_interface/tags/asyst_3/
96	Working.	mohor	7495d 17h	/dbg_interface/tags/asyst_3/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_3/] - Rev 121

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