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[/] [dbg_interface/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 128

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Rev Log message Author Age Path
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7495d 20h /dbg_interface/tags/asyst_3/rtl/verilog/
123 All flipflops are reset. mohor 7500d 16h /dbg_interface/tags/asyst_3/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7503d 16h /dbg_interface/tags/asyst_3/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7503d 20h /dbg_interface/tags/asyst_3/rtl/verilog/
117 Define name changed. mohor 7505d 16h /dbg_interface/tags/asyst_3/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7506d 23h /dbg_interface/tags/asyst_3/rtl/verilog/
106 Sensitivity list updated. simons 7507d 21h /dbg_interface/tags/asyst_3/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7508d 12h /dbg_interface/tags/asyst_3/rtl/verilog/
102 New version. mohor 7508d 12h /dbg_interface/tags/asyst_3/rtl/verilog/
101 Almost finished. mohor 7508d 13h /dbg_interface/tags/asyst_3/rtl/verilog/
100 *** empty log message *** mohor 7509d 15h /dbg_interface/tags/asyst_3/rtl/verilog/
99 cpu registers added. mohor 7509d 15h /dbg_interface/tags/asyst_3/rtl/verilog/
97 Working. mohor 7510d 18h /dbg_interface/tags/asyst_3/rtl/verilog/
95 Temp version. mohor 7511d 07h /dbg_interface/tags/asyst_3/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7511d 18h /dbg_interface/tags/asyst_3/rtl/verilog/
93 tmp version. mohor 7512d 19h /dbg_interface/tags/asyst_3/rtl/verilog/
92 temp version. mohor 7515d 22h /dbg_interface/tags/asyst_3/rtl/verilog/
91 tmp version. mohor 7516d 17h /dbg_interface/tags/asyst_3/rtl/verilog/
90 tmp version. mohor 7517d 12h /dbg_interface/tags/asyst_3/rtl/verilog/
89 temp4 version. mohor 7518d 18h /dbg_interface/tags/asyst_3/rtl/verilog/

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