OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 144

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
144 Port names and defines for the supported CPUs changed. igorm 7406d 13h /dbg_interface/tags/asyst_3/rtl/verilog/
143 Signals for easier debugging removed. igorm 7406d 15h /dbg_interface/tags/asyst_3/rtl/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7407d 10h /dbg_interface/tags/asyst_3/rtl/verilog/
139 New release of the debug interface (3rd. release). igorm 7410d 05h /dbg_interface/tags/asyst_3/rtl/verilog/
138 Temp version before changing dbg interface. igorm 7416d 08h /dbg_interface/tags/asyst_3/rtl/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7468d 15h /dbg_interface/tags/asyst_3/rtl/verilog/
123 All flipflops are reset. mohor 7473d 11h /dbg_interface/tags/asyst_3/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7476d 11h /dbg_interface/tags/asyst_3/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7476d 15h /dbg_interface/tags/asyst_3/rtl/verilog/
117 Define name changed. mohor 7478d 11h /dbg_interface/tags/asyst_3/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7479d 18h /dbg_interface/tags/asyst_3/rtl/verilog/
106 Sensitivity list updated. simons 7480d 16h /dbg_interface/tags/asyst_3/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7481d 06h /dbg_interface/tags/asyst_3/rtl/verilog/
102 New version. mohor 7481d 07h /dbg_interface/tags/asyst_3/rtl/verilog/
101 Almost finished. mohor 7481d 08h /dbg_interface/tags/asyst_3/rtl/verilog/
100 *** empty log message *** mohor 7482d 10h /dbg_interface/tags/asyst_3/rtl/verilog/
99 cpu registers added. mohor 7482d 10h /dbg_interface/tags/asyst_3/rtl/verilog/
97 Working. mohor 7483d 13h /dbg_interface/tags/asyst_3/rtl/verilog/
95 Temp version. mohor 7484d 02h /dbg_interface/tags/asyst_3/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7484d 13h /dbg_interface/tags/asyst_3/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.