OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] - Rev 36

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
36 Structure changed. Hooks for jtag chain added. mohor 8150d 01h /dbg_interface/tags/highland_ver1/
35 Dbg support datasheet added to cvs. mohor 8174d 06h /dbg_interface/tags/highland_ver1/
34 Product brief added to cvs. mohor 8175d 00h /dbg_interface/tags/highland_ver1/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8180d 04h /dbg_interface/tags/highland_ver1/
32 Stupid bug that was entered by previous update fixed. mohor 8181d 03h /dbg_interface/tags/highland_ver1/
31 trst synchronization is not needed and was removed. mohor 8181d 04h /dbg_interface/tags/highland_ver1/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8192d 09h /dbg_interface/tags/highland_ver1/
29 Document revised and put tp better form. mohor 8195d 22h /dbg_interface/tags/highland_ver1/
28 TDO and TDO Enable signal are separated into two signals. mohor 8228d 06h /dbg_interface/tags/highland_ver1/
27 Warnings from synthesys tools fixed. mohor 8242d 07h /dbg_interface/tags/highland_ver1/
26 Warnings from synthesys tools fixed. mohor 8242d 07h /dbg_interface/tags/highland_ver1/
25 trst signal is synchronized to wb_clk_i. mohor 8243d 03h /dbg_interface/tags/highland_ver1/
24 CRC changed so more thorough testing is done. mohor 8244d 05h /dbg_interface/tags/highland_ver1/
23 Trace disabled by default. mohor 8250d 07h /dbg_interface/tags/highland_ver1/
22 Register length fixed. mohor 8250d 07h /dbg_interface/tags/highland_ver1/
21 CRC is returned when chain selection data is transmitted. mohor 8251d 03h /dbg_interface/tags/highland_ver1/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8252d 06h /dbg_interface/tags/highland_ver1/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8264d 07h /dbg_interface/tags/highland_ver1/
18 Reset signals are not combined any more. mohor 8266d 16h /dbg_interface/tags/highland_ver1/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8290d 05h /dbg_interface/tags/highland_ver1/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.