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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5571d 03h	/dbg_interface/tags/highland_ver1/bench/
133	This commit was manufactured by cvs2svn to create tag 'highland_ver1'.		7393d 05h	/dbg_interface/tags/highland_ver1/bench/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7437d 13h	/dbg_interface/tags/highland_ver1/bench/
124	Display for VATS added.	mohor	7442d 09h	/dbg_interface/tags/highland_ver1/bench/
121	Port signals are all set to zero after reset.	mohor	7445d 09h	/dbg_interface/tags/highland_ver1/bench/
120	test stall_test added.	mohor	7445d 12h	/dbg_interface/tags/highland_ver1/bench/
117	Define name changed.	mohor	7447d 09h	/dbg_interface/tags/highland_ver1/bench/
116	Data latching changed when testing WB.	mohor	7447d 09h	/dbg_interface/tags/highland_ver1/bench/
115	More debug data added.	mohor	7447d 13h	/dbg_interface/tags/highland_ver1/bench/
114	CRC generation iand verification in bench changed.	mohor	7447d 14h	/dbg_interface/tags/highland_ver1/bench/
113	IDCODE test improved.	mohor	7447d 15h	/dbg_interface/tags/highland_ver1/bench/
112	dbg_tb_defines.v not used.	mohor	7448d 10h	/dbg_interface/tags/highland_ver1/bench/
111	Define tap_defines.v added to test bench.	mohor	7448d 10h	/dbg_interface/tags/highland_ver1/bench/
110	Waiting for "ready" improved.	mohor	7448d 10h	/dbg_interface/tags/highland_ver1/bench/
102	New version.	mohor	7450d 05h	/dbg_interface/tags/highland_ver1/bench/
101	Almost finished.	mohor	7450d 06h	/dbg_interface/tags/highland_ver1/bench/
99	cpu registers added.	mohor	7451d 08h	/dbg_interface/tags/highland_ver1/bench/
96	Working.	mohor	7452d 12h	/dbg_interface/tags/highland_ver1/bench/
95	Temp version.	mohor	7453d 00h	/dbg_interface/tags/highland_ver1/bench/
93	tmp version.	mohor	7454d 11h	/dbg_interface/tags/highland_ver1/bench/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] - Rev 158

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