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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] [verilog/] - Rev 112

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Rev Log message Author Age Path
112 dbg_tb_defines.v not used. mohor 7474d 14h /dbg_interface/tags/highland_ver1/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7474d 15h /dbg_interface/tags/highland_ver1/bench/verilog/
110 Waiting for "ready" improved. mohor 7474d 15h /dbg_interface/tags/highland_ver1/bench/verilog/
102 New version. mohor 7476d 10h /dbg_interface/tags/highland_ver1/bench/verilog/
101 Almost finished. mohor 7476d 11h /dbg_interface/tags/highland_ver1/bench/verilog/
99 cpu registers added. mohor 7477d 13h /dbg_interface/tags/highland_ver1/bench/verilog/
96 Working. mohor 7478d 17h /dbg_interface/tags/highland_ver1/bench/verilog/
95 Temp version. mohor 7479d 05h /dbg_interface/tags/highland_ver1/bench/verilog/
93 tmp version. mohor 7480d 16h /dbg_interface/tags/highland_ver1/bench/verilog/
92 temp version. mohor 7483d 20h /dbg_interface/tags/highland_ver1/bench/verilog/
91 tmp version. mohor 7484d 15h /dbg_interface/tags/highland_ver1/bench/verilog/
90 tmp version. mohor 7485d 10h /dbg_interface/tags/highland_ver1/bench/verilog/
89 temp4 version. mohor 7486d 16h /dbg_interface/tags/highland_ver1/bench/verilog/
88 temp3 version. mohor 7487d 11h /dbg_interface/tags/highland_ver1/bench/verilog/
87 tmp2 version. mohor 7488d 16h /dbg_interface/tags/highland_ver1/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7501d 13h /dbg_interface/tags/highland_ver1/bench/verilog/
75 Simulation files. mohor 7562d 11h /dbg_interface/tags/highland_ver1/bench/verilog/
73 CRC logic changed. mohor 7562d 12h /dbg_interface/tags/highland_ver1/bench/verilog/
63 Three more chains added for cpu debug access. simons 7618d 14h /dbg_interface/tags/highland_ver1/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8096d 13h /dbg_interface/tags/highland_ver1/bench/verilog/

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