OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] - Rev 158

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5571d 17h /dbg_interface/tags/highland_ver1/rtl/verilog/
133 This commit was manufactured by cvs2svn to create tag 'highland_ver1'. 7393d 19h /dbg_interface/tags/highland_ver1/rtl/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7438d 02h /dbg_interface/tags/highland_ver1/rtl/verilog/
123 All flipflops are reset. mohor 7442d 22h /dbg_interface/tags/highland_ver1/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7445d 23h /dbg_interface/tags/highland_ver1/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7446d 02h /dbg_interface/tags/highland_ver1/rtl/verilog/
117 Define name changed. mohor 7447d 22h /dbg_interface/tags/highland_ver1/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7449d 05h /dbg_interface/tags/highland_ver1/rtl/verilog/
106 Sensitivity list updated. simons 7450d 03h /dbg_interface/tags/highland_ver1/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7450d 18h /dbg_interface/tags/highland_ver1/rtl/verilog/
102 New version. mohor 7450d 18h /dbg_interface/tags/highland_ver1/rtl/verilog/
101 Almost finished. mohor 7450d 19h /dbg_interface/tags/highland_ver1/rtl/verilog/
100 *** empty log message *** mohor 7451d 22h /dbg_interface/tags/highland_ver1/rtl/verilog/
99 cpu registers added. mohor 7451d 22h /dbg_interface/tags/highland_ver1/rtl/verilog/
97 Working. mohor 7453d 00h /dbg_interface/tags/highland_ver1/rtl/verilog/
95 Temp version. mohor 7453d 14h /dbg_interface/tags/highland_ver1/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7454d 00h /dbg_interface/tags/highland_ver1/rtl/verilog/
93 tmp version. mohor 7455d 01h /dbg_interface/tags/highland_ver1/rtl/verilog/
92 temp version. mohor 7458d 05h /dbg_interface/tags/highland_ver1/rtl/verilog/
91 tmp version. mohor 7459d 00h /dbg_interface/tags/highland_ver1/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.