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[/] [dbg_interface/] [tags/] [old_debug/] [bench/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5590d 19h /dbg_interface/tags/old_debug/bench/verilog/
78 This commit was manufactured by cvs2svn to create tag 'old_debug'. 7555d 21h /dbg_interface/tags/old_debug/bench/verilog/
75 Simulation files. mohor 7555d 22h /dbg_interface/tags/old_debug/bench/verilog/
73 CRC logic changed. mohor 7555d 23h /dbg_interface/tags/old_debug/bench/verilog/
63 Three more chains added for cpu debug access. simons 7612d 01h /dbg_interface/tags/old_debug/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8090d 00h /dbg_interface/tags/old_debug/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8146d 00h /dbg_interface/tags/old_debug/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8149d 23h /dbg_interface/tags/old_debug/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8290d 03h /dbg_interface/tags/old_debug/bench/verilog/
15 bs_chain_o added. mohor 8292d 04h /dbg_interface/tags/old_debug/bench/verilog/
13 Signal names changed to lowercase. mohor 8293d 05h /dbg_interface/tags/old_debug/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8294d 05h /dbg_interface/tags/old_debug/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8315d 01h /dbg_interface/tags/old_debug/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8319d 05h /dbg_interface/tags/old_debug/bench/verilog/
6 Minor changes for simulation. mohor 8320d 03h /dbg_interface/tags/old_debug/bench/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8321d 01h /dbg_interface/tags/old_debug/bench/verilog/
2 Initial official release. mohor 8326d 01h /dbg_interface/tags/old_debug/bench/verilog/

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