URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [bench/] [verilog/] - Rev 17

Rev	Log message	Author	Age	Path
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8329d 06h	/dbg_interface/tags/old_debug/bench/verilog/
15	bs_chain_o added.	mohor	8331d 07h	/dbg_interface/tags/old_debug/bench/verilog/
13	Signal names changed to lowercase.	mohor	8332d 07h	/dbg_interface/tags/old_debug/bench/verilog/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8333d 07h	/dbg_interface/tags/old_debug/bench/verilog/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8354d 03h	/dbg_interface/tags/old_debug/bench/verilog/
9	Working version. Few bugs fixed, comments added.	mohor	8358d 07h	/dbg_interface/tags/old_debug/bench/verilog/
6	Minor changes for simulation.	mohor	8359d 06h	/dbg_interface/tags/old_debug/bench/verilog/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8360d 03h	/dbg_interface/tags/old_debug/bench/verilog/
2	Initial official release.	mohor	8365d 04h	/dbg_interface/tags/old_debug/bench/verilog/