OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Reset value for riscsel register set to 1. simons 7639d 23h /dbg_interface/tags/old_debug/rtl/verilog/
57 Multiple cpu support added. simons 7640d 00h /dbg_interface/tags/old_debug/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7906d 22h /dbg_interface/tags/old_debug/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7906d 22h /dbg_interface/tags/old_debug/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7934d 10h /dbg_interface/tags/old_debug/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 22h /dbg_interface/tags/old_debug/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8098d 04h /dbg_interface/tags/old_debug/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8105d 00h /dbg_interface/tags/old_debug/rtl/verilog/
44 Signal names changed to lower case. mohor 8105d 00h /dbg_interface/tags/old_debug/rtl/verilog/
43 Intentional error removed. mohor 8109d 23h /dbg_interface/tags/old_debug/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8110d 01h /dbg_interface/tags/old_debug/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8117d 22h /dbg_interface/tags/old_debug/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8131d 22h /dbg_interface/tags/old_debug/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8132d 23h /dbg_interface/tags/old_debug/rtl/verilog/
38 Few outputs for boundary scan chain added. mohor 8145d 22h /dbg_interface/tags/old_debug/rtl/verilog/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8146d 02h /dbg_interface/tags/old_debug/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8149d 21h /dbg_interface/tags/old_debug/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8180d 00h /dbg_interface/tags/old_debug/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8180d 23h /dbg_interface/tags/old_debug/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8181d 00h /dbg_interface/tags/old_debug/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.