OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] - Rev 77

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
77 MBIST chain connection fixed. mohor 7567d 06h /dbg_interface/tags/old_debug/rtl/verilog/
73 CRC logic changed. mohor 7567d 08h /dbg_interface/tags/old_debug/rtl/verilog/
71 Mbist support added. simons 7569d 14h /dbg_interface/tags/old_debug/rtl/verilog/
67 Lower two address lines must be always zero. simons 7602d 10h /dbg_interface/tags/old_debug/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7603d 09h /dbg_interface/tags/old_debug/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7623d 10h /dbg_interface/tags/old_debug/rtl/verilog/
61 Lapsus fixed. simons 7651d 10h /dbg_interface/tags/old_debug/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7651d 10h /dbg_interface/tags/old_debug/rtl/verilog/
57 Multiple cpu support added. simons 7651d 12h /dbg_interface/tags/old_debug/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7918d 09h /dbg_interface/tags/old_debug/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7918d 09h /dbg_interface/tags/old_debug/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7945d 21h /dbg_interface/tags/old_debug/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8101d 09h /dbg_interface/tags/old_debug/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8109d 15h /dbg_interface/tags/old_debug/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8116d 11h /dbg_interface/tags/old_debug/rtl/verilog/
44 Signal names changed to lower case. mohor 8116d 11h /dbg_interface/tags/old_debug/rtl/verilog/
43 Intentional error removed. mohor 8121d 11h /dbg_interface/tags/old_debug/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8121d 13h /dbg_interface/tags/old_debug/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8129d 10h /dbg_interface/tags/old_debug/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8143d 09h /dbg_interface/tags/old_debug/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.