URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] - Rev 17

Rev	Log message	Author	Age	Path
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8326d 06h	/dbg_interface/tags/rel_1/
16	bs_chain_o port added.	mohor	8328d 06h	/dbg_interface/tags/rel_1/
15	bs_chain_o added.	mohor	8328d 07h	/dbg_interface/tags/rel_1/
14	Document updated.	mohor	8329d 05h	/dbg_interface/tags/rel_1/
13	Signal names changed to lowercase.	mohor	8329d 08h	/dbg_interface/tags/rel_1/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8330d 08h	/dbg_interface/tags/rel_1/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8351d 04h	/dbg_interface/tags/rel_1/
10	First official release 1.0.	mohor	8355d 08h	/dbg_interface/tags/rel_1/
9	Working version. Few bugs fixed, comments added.	mohor	8355d 08h	/dbg_interface/tags/rel_1/
8	Asynchronous set/reset not used in trace any more.	mohor	8356d 06h	/dbg_interface/tags/rel_1/
7	First official release 1.0.	mohor	8356d 06h	/dbg_interface/tags/rel_1/
6	Minor changes for simulation.	mohor	8356d 06h	/dbg_interface/tags/rel_1/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8357d 04h	/dbg_interface/tags/rel_1/
4	Initial official release.	mohor	8362d 04h	/dbg_interface/tags/rel_1/
2	Initial official release.	mohor	8362d 04h	/dbg_interface/tags/rel_1/
1	Standard project directories initialized by cvs2svn.		8362d 04h	/dbg_interface/tags/rel_1/