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[/] [dbg_interface/] [tags/] [rel_1/] - Rev 28

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Rev Log message Author Age Path
28 TDO and TDO Enable signal are separated into two signals. mohor 8223d 07h /dbg_interface/tags/rel_1/
27 Warnings from synthesys tools fixed. mohor 8237d 08h /dbg_interface/tags/rel_1/
26 Warnings from synthesys tools fixed. mohor 8237d 08h /dbg_interface/tags/rel_1/
25 trst signal is synchronized to wb_clk_i. mohor 8238d 05h /dbg_interface/tags/rel_1/
24 CRC changed so more thorough testing is done. mohor 8239d 06h /dbg_interface/tags/rel_1/
23 Trace disabled by default. mohor 8245d 09h /dbg_interface/tags/rel_1/
22 Register length fixed. mohor 8245d 09h /dbg_interface/tags/rel_1/
21 CRC is returned when chain selection data is transmitted. mohor 8246d 05h /dbg_interface/tags/rel_1/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8247d 07h /dbg_interface/tags/rel_1/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8259d 08h /dbg_interface/tags/rel_1/
18 Reset signals are not combined any more. mohor 8261d 17h /dbg_interface/tags/rel_1/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8285d 07h /dbg_interface/tags/rel_1/
16 bs_chain_o port added. mohor 8287d 06h /dbg_interface/tags/rel_1/
15 bs_chain_o added. mohor 8287d 08h /dbg_interface/tags/rel_1/
14 Document updated. mohor 8288d 05h /dbg_interface/tags/rel_1/
13 Signal names changed to lowercase. mohor 8288d 08h /dbg_interface/tags/rel_1/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8289d 08h /dbg_interface/tags/rel_1/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8310d 04h /dbg_interface/tags/rel_1/
10 First official release 1.0. mohor 8314d 08h /dbg_interface/tags/rel_1/
9 Working version. Few bugs fixed, comments added. mohor 8314d 08h /dbg_interface/tags/rel_1/

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