OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 31

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
31 trst synchronization is not needed and was removed. mohor 8177d 01h /dbg_interface/tags/rel_1/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8188d 06h /dbg_interface/tags/rel_1/rtl/verilog/
28 TDO and TDO Enable signal are separated into two signals. mohor 8224d 02h /dbg_interface/tags/rel_1/rtl/verilog/
27 Warnings from synthesys tools fixed. mohor 8238d 04h /dbg_interface/tags/rel_1/rtl/verilog/
26 Warnings from synthesys tools fixed. mohor 8238d 04h /dbg_interface/tags/rel_1/rtl/verilog/
25 trst signal is synchronized to wb_clk_i. mohor 8239d 00h /dbg_interface/tags/rel_1/rtl/verilog/
23 Trace disabled by default. mohor 8246d 04h /dbg_interface/tags/rel_1/rtl/verilog/
22 Register length fixed. mohor 8246d 04h /dbg_interface/tags/rel_1/rtl/verilog/
21 CRC is returned when chain selection data is transmitted. mohor 8247d 00h /dbg_interface/tags/rel_1/rtl/verilog/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8248d 03h /dbg_interface/tags/rel_1/rtl/verilog/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8260d 03h /dbg_interface/tags/rel_1/rtl/verilog/
18 Reset signals are not combined any more. mohor 8262d 12h /dbg_interface/tags/rel_1/rtl/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8286d 02h /dbg_interface/tags/rel_1/rtl/verilog/
15 bs_chain_o added. mohor 8288d 03h /dbg_interface/tags/rel_1/rtl/verilog/
13 Signal names changed to lowercase. mohor 8289d 04h /dbg_interface/tags/rel_1/rtl/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8290d 04h /dbg_interface/tags/rel_1/rtl/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8311d 00h /dbg_interface/tags/rel_1/rtl/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8315d 03h /dbg_interface/tags/rel_1/rtl/verilog/
8 Asynchronous set/reset not used in trace any more. mohor 8316d 02h /dbg_interface/tags/rel_1/rtl/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8316d 23h /dbg_interface/tags/rel_1/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.