OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 45

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8101d 01h /dbg_interface/tags/rel_1/rtl/verilog/
44 Signal names changed to lower case. mohor 8101d 01h /dbg_interface/tags/rel_1/rtl/verilog/
43 Intentional error removed. mohor 8106d 00h /dbg_interface/tags/rel_1/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8106d 02h /dbg_interface/tags/rel_1/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8113d 23h /dbg_interface/tags/rel_1/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8127d 23h /dbg_interface/tags/rel_1/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8129d 00h /dbg_interface/tags/rel_1/rtl/verilog/
38 Few outputs for boundary scan chain added. mohor 8141d 23h /dbg_interface/tags/rel_1/rtl/verilog/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8142d 03h /dbg_interface/tags/rel_1/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8145d 22h /dbg_interface/tags/rel_1/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8176d 01h /dbg_interface/tags/rel_1/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8177d 00h /dbg_interface/tags/rel_1/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8177d 01h /dbg_interface/tags/rel_1/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8188d 06h /dbg_interface/tags/rel_1/rtl/verilog/
28 TDO and TDO Enable signal are separated into two signals. mohor 8224d 02h /dbg_interface/tags/rel_1/rtl/verilog/
27 Warnings from synthesys tools fixed. mohor 8238d 03h /dbg_interface/tags/rel_1/rtl/verilog/
26 Warnings from synthesys tools fixed. mohor 8238d 03h /dbg_interface/tags/rel_1/rtl/verilog/
25 trst signal is synchronized to wb_clk_i. mohor 8239d 00h /dbg_interface/tags/rel_1/rtl/verilog/
23 Trace disabled by default. mohor 8246d 04h /dbg_interface/tags/rel_1/rtl/verilog/
22 Register length fixed. mohor 8246d 04h /dbg_interface/tags/rel_1/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.