URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [sim/] [rtl_sim/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5586d 20h	/dbg_interface/tags/rel_1/sim/rtl_sim/
48	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8086d 01h	/dbg_interface/tags/rel_1/sim/rtl_sim/
36	Structure changed. Hooks for jtag chain added.	mohor	8146d 00h	/dbg_interface/tags/rel_1/sim/rtl_sim/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8286d 04h	/dbg_interface/tags/rel_1/sim/rtl_sim/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8317d 02h	/dbg_interface/tags/rel_1/sim/rtl_sim/
2	Initial official release.	mohor	8322d 02h	/dbg_interface/tags/rel_1/sim/rtl_sim/