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[/] [dbg_interface/] [tags/] [rel_1/] [sim/] [rtl_sim/] - Rev 17

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Rev Log message Author Age Path
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8306d 23h /dbg_interface/tags/rel_1/sim/rtl_sim/
5 Trace fixed. Some registers changed, trace simplified. mohor 8337d 20h /dbg_interface/tags/rel_1/sim/rtl_sim/
2 Initial official release. mohor 8342d 21h /dbg_interface/tags/rel_1/sim/rtl_sim/

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