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[/] [dbg_interface/] [tags/] [rel_10/] - Rev 29

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Rev Log message Author Age Path
29 Document revised and put tp better form. mohor 8207d 06h /dbg_interface/tags/rel_10/
28 TDO and TDO Enable signal are separated into two signals. mohor 8239d 14h /dbg_interface/tags/rel_10/
27 Warnings from synthesys tools fixed. mohor 8253d 15h /dbg_interface/tags/rel_10/
26 Warnings from synthesys tools fixed. mohor 8253d 15h /dbg_interface/tags/rel_10/
25 trst signal is synchronized to wb_clk_i. mohor 8254d 11h /dbg_interface/tags/rel_10/
24 CRC changed so more thorough testing is done. mohor 8255d 13h /dbg_interface/tags/rel_10/
23 Trace disabled by default. mohor 8261d 15h /dbg_interface/tags/rel_10/
22 Register length fixed. mohor 8261d 15h /dbg_interface/tags/rel_10/
21 CRC is returned when chain selection data is transmitted. mohor 8262d 11h /dbg_interface/tags/rel_10/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8263d 14h /dbg_interface/tags/rel_10/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8275d 15h /dbg_interface/tags/rel_10/
18 Reset signals are not combined any more. mohor 8278d 00h /dbg_interface/tags/rel_10/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8301d 13h /dbg_interface/tags/rel_10/
16 bs_chain_o port added. mohor 8303d 13h /dbg_interface/tags/rel_10/
15 bs_chain_o added. mohor 8303d 14h /dbg_interface/tags/rel_10/
14 Document updated. mohor 8304d 12h /dbg_interface/tags/rel_10/
13 Signal names changed to lowercase. mohor 8304d 15h /dbg_interface/tags/rel_10/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8305d 15h /dbg_interface/tags/rel_10/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8326d 11h /dbg_interface/tags/rel_10/
10 First official release 1.0. mohor 8330d 15h /dbg_interface/tags/rel_10/

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