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[/] [dbg_interface/] [tags/] [rel_10/] [bench/] - Rev 158

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Rev Log message Author Age Path
158 root 5567d 22h /dbg_interface/tags/rel_10/bench/
76 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7533d 02h /dbg_interface/tags/rel_10/bench/
75 Simulation files. mohor 7533d 02h /dbg_interface/tags/rel_10/bench/
73 CRC logic changed. mohor 7533d 02h /dbg_interface/tags/rel_10/bench/
63 Three more chains added for cpu debug access. simons 7589d 04h /dbg_interface/tags/rel_10/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8067d 03h /dbg_interface/tags/rel_10/bench/
38 Few outputs for boundary scan chain added. mohor 8123d 04h /dbg_interface/tags/rel_10/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8127d 03h /dbg_interface/tags/rel_10/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8267d 06h /dbg_interface/tags/rel_10/bench/
15 bs_chain_o added. mohor 8269d 07h /dbg_interface/tags/rel_10/bench/
13 Signal names changed to lowercase. mohor 8270d 08h /dbg_interface/tags/rel_10/bench/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8271d 08h /dbg_interface/tags/rel_10/bench/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8292d 04h /dbg_interface/tags/rel_10/bench/
9 Working version. Few bugs fixed, comments added. mohor 8296d 08h /dbg_interface/tags/rel_10/bench/
6 Minor changes for simulation. mohor 8297d 06h /dbg_interface/tags/rel_10/bench/
5 Trace fixed. Some registers changed, trace simplified. mohor 8298d 04h /dbg_interface/tags/rel_10/bench/
2 Initial official release. mohor 8303d 04h /dbg_interface/tags/rel_10/bench/

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