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[/] [dbg_interface/] [tags/] [rel_10/] [rtl/] - Rev 67

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Rev Log message Author Age Path
67 Lower two address lines must be always zero. simons 7590d 06h /dbg_interface/tags/rel_10/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7591d 06h /dbg_interface/tags/rel_10/rtl/
63 Three more chains added for cpu debug access. simons 7611d 06h /dbg_interface/tags/rel_10/rtl/
61 Lapsus fixed. simons 7639d 06h /dbg_interface/tags/rel_10/rtl/
59 Reset value for riscsel register set to 1. simons 7639d 06h /dbg_interface/tags/rel_10/rtl/
57 Multiple cpu support added. simons 7639d 08h /dbg_interface/tags/rel_10/rtl/
53 Trst active high. Inverted on higher layer. mohor 7906d 06h /dbg_interface/tags/rel_10/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7906d 06h /dbg_interface/tags/rel_10/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7933d 17h /dbg_interface/tags/rel_10/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 05h /dbg_interface/tags/rel_10/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8097d 12h /dbg_interface/tags/rel_10/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8104d 07h /dbg_interface/tags/rel_10/rtl/
44 Signal names changed to lower case. mohor 8104d 07h /dbg_interface/tags/rel_10/rtl/
43 Intentional error removed. mohor 8109d 07h /dbg_interface/tags/rel_10/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8109d 09h /dbg_interface/tags/rel_10/rtl/
41 Function changed to logic because of some synthesis warnings. mohor 8117d 06h /dbg_interface/tags/rel_10/rtl/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8131d 06h /dbg_interface/tags/rel_10/rtl/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8132d 07h /dbg_interface/tags/rel_10/rtl/
38 Few outputs for boundary scan chain added. mohor 8145d 06h /dbg_interface/tags/rel_10/rtl/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8145d 10h /dbg_interface/tags/rel_10/rtl/

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