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[/] [dbg_interface/] [tags/] [rel_12/] - Rev 84

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Rev Log message Author Age Path
84 Removed files that are not needed any more. mohor 7606d 16h /dbg_interface/tags/rel_12/
83 Small fix. mohor 7606d 16h /dbg_interface/tags/rel_12/
82 New directory structure. New version of the debug interface. mohor 7606d 17h /dbg_interface/tags/rel_12/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7606d 17h /dbg_interface/tags/rel_12/
80 New version of the debug interface. Not finished, yet. mohor 7606d 17h /dbg_interface/tags/rel_12/
77 MBIST chain connection fixed. mohor 7667d 14h /dbg_interface/tags/rel_12/
75 Simulation files. mohor 7667d 15h /dbg_interface/tags/rel_12/
74 Removed. mohor 7667d 15h /dbg_interface/tags/rel_12/
73 CRC logic changed. mohor 7667d 16h /dbg_interface/tags/rel_12/
71 Mbist support added. simons 7669d 22h /dbg_interface/tags/rel_12/
70 A pdf copy of existing doc document. simons 7677d 00h /dbg_interface/tags/rel_12/
69 WBCNTL added, multiple CPU support described. simons 7697d 13h /dbg_interface/tags/rel_12/
67 Lower two address lines must be always zero. simons 7702d 18h /dbg_interface/tags/rel_12/
65 WB_CNTL register added, some syncronization fixes. simons 7703d 17h /dbg_interface/tags/rel_12/
63 Three more chains added for cpu debug access. simons 7723d 18h /dbg_interface/tags/rel_12/
61 Lapsus fixed. simons 7751d 18h /dbg_interface/tags/rel_12/
59 Reset value for riscsel register set to 1. simons 7751d 18h /dbg_interface/tags/rel_12/
57 Multiple cpu support added. simons 7751d 20h /dbg_interface/tags/rel_12/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8018d 16h /dbg_interface/tags/rel_12/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8018d 16h /dbg_interface/tags/rel_12/

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