URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_12/] [bench/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5586d 21h	/dbg_interface/tags/rel_12/bench/
103	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7465d 23h	/dbg_interface/tags/rel_12/bench/
102	New version.	mohor	7465d 23h	/dbg_interface/tags/rel_12/bench/
101	Almost finished.	mohor	7466d 00h	/dbg_interface/tags/rel_12/bench/
99	cpu registers added.	mohor	7467d 02h	/dbg_interface/tags/rel_12/bench/
96	Working.	mohor	7468d 06h	/dbg_interface/tags/rel_12/bench/
95	Temp version.	mohor	7468d 18h	/dbg_interface/tags/rel_12/bench/
93	tmp version.	mohor	7470d 05h	/dbg_interface/tags/rel_12/bench/
92	temp version.	mohor	7473d 09h	/dbg_interface/tags/rel_12/bench/
91	tmp version.	mohor	7474d 04h	/dbg_interface/tags/rel_12/bench/
90	tmp version.	mohor	7474d 23h	/dbg_interface/tags/rel_12/bench/
89	temp4 version.	mohor	7476d 05h	/dbg_interface/tags/rel_12/bench/
88	temp3 version.	mohor	7476d 23h	/dbg_interface/tags/rel_12/bench/
87	tmp2 version.	mohor	7478d 04h	/dbg_interface/tags/rel_12/bench/
80	New version of the debug interface. Not finished, yet.	mohor	7491d 02h	/dbg_interface/tags/rel_12/bench/
75	Simulation files.	mohor	7552d 00h	/dbg_interface/tags/rel_12/bench/
73	CRC logic changed.	mohor	7552d 00h	/dbg_interface/tags/rel_12/bench/
63	Three more chains added for cpu debug access.	simons	7608d 03h	/dbg_interface/tags/rel_12/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8086d 02h	/dbg_interface/tags/rel_12/bench/
38	Few outputs for boundary scan chain added.	mohor	8142d 02h	/dbg_interface/tags/rel_12/bench/