URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_12/] [bench/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5602d 04h	/dbg_interface/tags/rel_12/bench/
103	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7481d 06h	/dbg_interface/tags/rel_12/bench/
102	New version.	mohor	7481d 06h	/dbg_interface/tags/rel_12/bench/
101	Almost finished.	mohor	7481d 07h	/dbg_interface/tags/rel_12/bench/
99	cpu registers added.	mohor	7482d 09h	/dbg_interface/tags/rel_12/bench/
96	Working.	mohor	7483d 13h	/dbg_interface/tags/rel_12/bench/
95	Temp version.	mohor	7484d 01h	/dbg_interface/tags/rel_12/bench/
93	tmp version.	mohor	7485d 12h	/dbg_interface/tags/rel_12/bench/
92	temp version.	mohor	7488d 16h	/dbg_interface/tags/rel_12/bench/
91	tmp version.	mohor	7489d 11h	/dbg_interface/tags/rel_12/bench/
90	tmp version.	mohor	7490d 06h	/dbg_interface/tags/rel_12/bench/
89	temp4 version.	mohor	7491d 12h	/dbg_interface/tags/rel_12/bench/
88	temp3 version.	mohor	7492d 06h	/dbg_interface/tags/rel_12/bench/
87	tmp2 version.	mohor	7493d 11h	/dbg_interface/tags/rel_12/bench/
80	New version of the debug interface. Not finished, yet.	mohor	7506d 09h	/dbg_interface/tags/rel_12/bench/
75	Simulation files.	mohor	7567d 07h	/dbg_interface/tags/rel_12/bench/
73	CRC logic changed.	mohor	7567d 07h	/dbg_interface/tags/rel_12/bench/
63	Three more chains added for cpu debug access.	simons	7623d 10h	/dbg_interface/tags/rel_12/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8101d 09h	/dbg_interface/tags/rel_12/bench/
38	Few outputs for boundary scan chain added.	mohor	8157d 09h	/dbg_interface/tags/rel_12/bench/