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[/] [dbg_interface/] [tags/] [rel_12/] [bench/] - Rev 99

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Rev Log message Author Age Path
99 cpu registers added. mohor 7487d 20h /dbg_interface/tags/rel_12/bench/
96 Working. mohor 7489d 00h /dbg_interface/tags/rel_12/bench/
95 Temp version. mohor 7489d 12h /dbg_interface/tags/rel_12/bench/
93 tmp version. mohor 7490d 23h /dbg_interface/tags/rel_12/bench/
92 temp version. mohor 7494d 03h /dbg_interface/tags/rel_12/bench/
91 tmp version. mohor 7494d 22h /dbg_interface/tags/rel_12/bench/
90 tmp version. mohor 7495d 17h /dbg_interface/tags/rel_12/bench/
89 temp4 version. mohor 7496d 23h /dbg_interface/tags/rel_12/bench/
88 temp3 version. mohor 7497d 17h /dbg_interface/tags/rel_12/bench/
87 tmp2 version. mohor 7498d 22h /dbg_interface/tags/rel_12/bench/
80 New version of the debug interface. Not finished, yet. mohor 7511d 20h /dbg_interface/tags/rel_12/bench/
75 Simulation files. mohor 7572d 18h /dbg_interface/tags/rel_12/bench/
73 CRC logic changed. mohor 7572d 18h /dbg_interface/tags/rel_12/bench/
63 Three more chains added for cpu debug access. simons 7628d 21h /dbg_interface/tags/rel_12/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8106d 20h /dbg_interface/tags/rel_12/bench/
38 Few outputs for boundary scan chain added. mohor 8162d 20h /dbg_interface/tags/rel_12/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8166d 19h /dbg_interface/tags/rel_12/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8306d 23h /dbg_interface/tags/rel_12/bench/
15 bs_chain_o added. mohor 8309d 00h /dbg_interface/tags/rel_12/bench/
13 Signal names changed to lowercase. mohor 8310d 00h /dbg_interface/tags/rel_12/bench/

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