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[/] [dbg_interface/] [tags/] [rel_13/] [bench/] - Rev 99

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Rev Log message Author Age Path
99 cpu registers added. mohor 7528d 04h /dbg_interface/tags/rel_13/bench/
96 Working. mohor 7529d 09h /dbg_interface/tags/rel_13/bench/
95 Temp version. mohor 7529d 20h /dbg_interface/tags/rel_13/bench/
93 tmp version. mohor 7531d 08h /dbg_interface/tags/rel_13/bench/
92 temp version. mohor 7534d 11h /dbg_interface/tags/rel_13/bench/
91 tmp version. mohor 7535d 06h /dbg_interface/tags/rel_13/bench/
90 tmp version. mohor 7536d 01h /dbg_interface/tags/rel_13/bench/
89 temp4 version. mohor 7537d 07h /dbg_interface/tags/rel_13/bench/
88 temp3 version. mohor 7538d 02h /dbg_interface/tags/rel_13/bench/
87 tmp2 version. mohor 7539d 07h /dbg_interface/tags/rel_13/bench/
80 New version of the debug interface. Not finished, yet. mohor 7552d 05h /dbg_interface/tags/rel_13/bench/
75 Simulation files. mohor 7613d 03h /dbg_interface/tags/rel_13/bench/
73 CRC logic changed. mohor 7613d 03h /dbg_interface/tags/rel_13/bench/
63 Three more chains added for cpu debug access. simons 7669d 05h /dbg_interface/tags/rel_13/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8147d 05h /dbg_interface/tags/rel_13/bench/
38 Few outputs for boundary scan chain added. mohor 8203d 05h /dbg_interface/tags/rel_13/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8207d 04h /dbg_interface/tags/rel_13/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8347d 08h /dbg_interface/tags/rel_13/bench/
15 bs_chain_o added. mohor 8349d 09h /dbg_interface/tags/rel_13/bench/
13 Signal names changed to lowercase. mohor 8350d 09h /dbg_interface/tags/rel_13/bench/

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