OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_14/] - Rev 84

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
84 Removed files that are not needed any more. mohor 7491d 03h /dbg_interface/tags/rel_14/
83 Small fix. mohor 7491d 03h /dbg_interface/tags/rel_14/
82 New directory structure. New version of the debug interface. mohor 7491d 03h /dbg_interface/tags/rel_14/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7491d 03h /dbg_interface/tags/rel_14/
80 New version of the debug interface. Not finished, yet. mohor 7491d 04h /dbg_interface/tags/rel_14/
77 MBIST chain connection fixed. mohor 7552d 00h /dbg_interface/tags/rel_14/
75 Simulation files. mohor 7552d 02h /dbg_interface/tags/rel_14/
74 Removed. mohor 7552d 02h /dbg_interface/tags/rel_14/
73 CRC logic changed. mohor 7552d 02h /dbg_interface/tags/rel_14/
71 Mbist support added. simons 7554d 09h /dbg_interface/tags/rel_14/
70 A pdf copy of existing doc document. simons 7561d 10h /dbg_interface/tags/rel_14/
69 WBCNTL added, multiple CPU support described. simons 7582d 00h /dbg_interface/tags/rel_14/
67 Lower two address lines must be always zero. simons 7587d 04h /dbg_interface/tags/rel_14/
65 WB_CNTL register added, some syncronization fixes. simons 7588d 04h /dbg_interface/tags/rel_14/
63 Three more chains added for cpu debug access. simons 7608d 04h /dbg_interface/tags/rel_14/
61 Lapsus fixed. simons 7636d 04h /dbg_interface/tags/rel_14/
59 Reset value for riscsel register set to 1. simons 7636d 05h /dbg_interface/tags/rel_14/
57 Multiple cpu support added. simons 7636d 06h /dbg_interface/tags/rel_14/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7903d 02h /dbg_interface/tags/rel_14/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7903d 02h /dbg_interface/tags/rel_14/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.