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[/] [dbg_interface/] [tags/] [rel_15/] - Rev 25

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Rev Log message Author Age Path
25 trst signal is synchronized to wb_clk_i. mohor 8249d 22h /dbg_interface/tags/rel_15/
24 CRC changed so more thorough testing is done. mohor 8251d 00h /dbg_interface/tags/rel_15/
23 Trace disabled by default. mohor 8257d 02h /dbg_interface/tags/rel_15/
22 Register length fixed. mohor 8257d 02h /dbg_interface/tags/rel_15/
21 CRC is returned when chain selection data is transmitted. mohor 8257d 22h /dbg_interface/tags/rel_15/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8259d 01h /dbg_interface/tags/rel_15/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8271d 02h /dbg_interface/tags/rel_15/
18 Reset signals are not combined any more. mohor 8273d 11h /dbg_interface/tags/rel_15/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8297d 00h /dbg_interface/tags/rel_15/
16 bs_chain_o port added. mohor 8299d 00h /dbg_interface/tags/rel_15/
15 bs_chain_o added. mohor 8299d 01h /dbg_interface/tags/rel_15/
14 Document updated. mohor 8299d 23h /dbg_interface/tags/rel_15/
13 Signal names changed to lowercase. mohor 8300d 02h /dbg_interface/tags/rel_15/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8301d 02h /dbg_interface/tags/rel_15/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8321d 22h /dbg_interface/tags/rel_15/
10 First official release 1.0. mohor 8326d 02h /dbg_interface/tags/rel_15/
9 Working version. Few bugs fixed, comments added. mohor 8326d 02h /dbg_interface/tags/rel_15/
8 Asynchronous set/reset not used in trace any more. mohor 8327d 00h /dbg_interface/tags/rel_15/
7 First official release 1.0. mohor 8327d 00h /dbg_interface/tags/rel_15/
6 Minor changes for simulation. mohor 8327d 00h /dbg_interface/tags/rel_15/

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