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[/] [dbg_interface/] [tags/] [rel_15/] - Rev 86

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Rev Log message Author Age Path
86 Tmp version. mohor 7493d 19h /dbg_interface/tags/rel_15/
85 New directory structure. New debug interface. mohor 7493d 20h /dbg_interface/tags/rel_15/
84 Removed files that are not needed any more. mohor 7493d 20h /dbg_interface/tags/rel_15/
83 Small fix. mohor 7493d 20h /dbg_interface/tags/rel_15/
82 New directory structure. New version of the debug interface. mohor 7493d 20h /dbg_interface/tags/rel_15/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7493d 20h /dbg_interface/tags/rel_15/
80 New version of the debug interface. Not finished, yet. mohor 7493d 21h /dbg_interface/tags/rel_15/
77 MBIST chain connection fixed. mohor 7554d 17h /dbg_interface/tags/rel_15/
75 Simulation files. mohor 7554d 19h /dbg_interface/tags/rel_15/
74 Removed. mohor 7554d 19h /dbg_interface/tags/rel_15/
73 CRC logic changed. mohor 7554d 19h /dbg_interface/tags/rel_15/
71 Mbist support added. simons 7557d 02h /dbg_interface/tags/rel_15/
70 A pdf copy of existing doc document. simons 7564d 03h /dbg_interface/tags/rel_15/
69 WBCNTL added, multiple CPU support described. simons 7584d 17h /dbg_interface/tags/rel_15/
67 Lower two address lines must be always zero. simons 7589d 21h /dbg_interface/tags/rel_15/
65 WB_CNTL register added, some syncronization fixes. simons 7590d 21h /dbg_interface/tags/rel_15/
63 Three more chains added for cpu debug access. simons 7610d 21h /dbg_interface/tags/rel_15/
61 Lapsus fixed. simons 7638d 21h /dbg_interface/tags/rel_15/
59 Reset value for riscsel register set to 1. simons 7638d 22h /dbg_interface/tags/rel_15/
57 Multiple cpu support added. simons 7638d 23h /dbg_interface/tags/rel_15/

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