OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] - Rev 90

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
90 tmp version. mohor 7477d 18h /dbg_interface/tags/rel_15/
89 temp4 version. mohor 7479d 00h /dbg_interface/tags/rel_15/
88 temp3 version. mohor 7479d 18h /dbg_interface/tags/rel_15/
87 tmp2 version. mohor 7480d 23h /dbg_interface/tags/rel_15/
86 Tmp version. mohor 7493d 19h /dbg_interface/tags/rel_15/
85 New directory structure. New debug interface. mohor 7493d 20h /dbg_interface/tags/rel_15/
84 Removed files that are not needed any more. mohor 7493d 20h /dbg_interface/tags/rel_15/
83 Small fix. mohor 7493d 20h /dbg_interface/tags/rel_15/
82 New directory structure. New version of the debug interface. mohor 7493d 20h /dbg_interface/tags/rel_15/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7493d 20h /dbg_interface/tags/rel_15/
80 New version of the debug interface. Not finished, yet. mohor 7493d 21h /dbg_interface/tags/rel_15/
77 MBIST chain connection fixed. mohor 7554d 17h /dbg_interface/tags/rel_15/
75 Simulation files. mohor 7554d 19h /dbg_interface/tags/rel_15/
74 Removed. mohor 7554d 19h /dbg_interface/tags/rel_15/
73 CRC logic changed. mohor 7554d 19h /dbg_interface/tags/rel_15/
71 Mbist support added. simons 7557d 02h /dbg_interface/tags/rel_15/
70 A pdf copy of existing doc document. simons 7564d 04h /dbg_interface/tags/rel_15/
69 WBCNTL added, multiple CPU support described. simons 7584d 17h /dbg_interface/tags/rel_15/
67 Lower two address lines must be always zero. simons 7589d 22h /dbg_interface/tags/rel_15/
65 WB_CNTL register added, some syncronization fixes. simons 7590d 21h /dbg_interface/tags/rel_15/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.