URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [bench/] - Rev 73

Rev	Log message	Author	Age	Path
73	CRC logic changed.	mohor	7562d 12h	/dbg_interface/tags/rel_15/bench/
63	Three more chains added for cpu debug access.	simons	7618d 14h	/dbg_interface/tags/rel_15/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8096d 13h	/dbg_interface/tags/rel_15/bench/
38	Few outputs for boundary scan chain added.	mohor	8152d 13h	/dbg_interface/tags/rel_15/bench/
36	Structure changed. Hooks for jtag chain added.	mohor	8156d 12h	/dbg_interface/tags/rel_15/bench/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8296d 16h	/dbg_interface/tags/rel_15/bench/
15	bs_chain_o added.	mohor	8298d 17h	/dbg_interface/tags/rel_15/bench/
13	Signal names changed to lowercase.	mohor	8299d 18h	/dbg_interface/tags/rel_15/bench/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8300d 18h	/dbg_interface/tags/rel_15/bench/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8321d 14h	/dbg_interface/tags/rel_15/bench/
9	Working version. Few bugs fixed, comments added.	mohor	8325d 18h	/dbg_interface/tags/rel_15/bench/
6	Minor changes for simulation.	mohor	8326d 16h	/dbg_interface/tags/rel_15/bench/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8327d 14h	/dbg_interface/tags/rel_15/bench/
2	Initial official release.	mohor	8332d 14h	/dbg_interface/tags/rel_15/bench/