URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] - Rev 94

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Rev	Log message	Author	Age	Path
94	temp version. Resets will be changed in next version.	mohor	7468d 08h	/dbg_interface/tags/rel_15/rtl/
93	tmp version.	mohor	7469d 09h	/dbg_interface/tags/rel_15/rtl/
92	temp version.	mohor	7472d 13h	/dbg_interface/tags/rel_15/rtl/
91	tmp version.	mohor	7473d 08h	/dbg_interface/tags/rel_15/rtl/
90	tmp version.	mohor	7474d 02h	/dbg_interface/tags/rel_15/rtl/
89	temp4 version.	mohor	7475d 08h	/dbg_interface/tags/rel_15/rtl/
88	temp3 version.	mohor	7476d 03h	/dbg_interface/tags/rel_15/rtl/
87	tmp2 version.	mohor	7477d 08h	/dbg_interface/tags/rel_15/rtl/
86	Tmp version.	mohor	7490d 04h	/dbg_interface/tags/rel_15/rtl/
83	Small fix.	mohor	7490d 05h	/dbg_interface/tags/rel_15/rtl/
82	New directory structure. New version of the debug interface.	mohor	7490d 05h	/dbg_interface/tags/rel_15/rtl/
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7490d 05h	/dbg_interface/tags/rel_15/rtl/
77	MBIST chain connection fixed.	mohor	7551d 02h	/dbg_interface/tags/rel_15/rtl/
73	CRC logic changed.	mohor	7551d 04h	/dbg_interface/tags/rel_15/rtl/
71	Mbist support added.	simons	7553d 11h	/dbg_interface/tags/rel_15/rtl/
67	Lower two address lines must be always zero.	simons	7586d 06h	/dbg_interface/tags/rel_15/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7587d 06h	/dbg_interface/tags/rel_15/rtl/
63	Three more chains added for cpu debug access.	simons	7607d 06h	/dbg_interface/tags/rel_15/rtl/
61	Lapsus fixed.	simons	7635d 06h	/dbg_interface/tags/rel_15/rtl/
59	Reset value for riscsel register set to 1.	simons	7635d 07h	/dbg_interface/tags/rel_15/rtl/

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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] - Rev 94

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