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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 81

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Rev Log message Author Age Path
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7541d 08h /dbg_interface/tags/rel_15/rtl/verilog/
77 MBIST chain connection fixed. mohor 7602d 05h /dbg_interface/tags/rel_15/rtl/verilog/
73 CRC logic changed. mohor 7602d 07h /dbg_interface/tags/rel_15/rtl/verilog/
71 Mbist support added. simons 7604d 13h /dbg_interface/tags/rel_15/rtl/verilog/
67 Lower two address lines must be always zero. simons 7637d 09h /dbg_interface/tags/rel_15/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7638d 08h /dbg_interface/tags/rel_15/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7658d 09h /dbg_interface/tags/rel_15/rtl/verilog/
61 Lapsus fixed. simons 7686d 09h /dbg_interface/tags/rel_15/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7686d 09h /dbg_interface/tags/rel_15/rtl/verilog/
57 Multiple cpu support added. simons 7686d 11h /dbg_interface/tags/rel_15/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7953d 08h /dbg_interface/tags/rel_15/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7953d 09h /dbg_interface/tags/rel_15/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7980d 20h /dbg_interface/tags/rel_15/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8136d 08h /dbg_interface/tags/rel_15/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8144d 14h /dbg_interface/tags/rel_15/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8151d 10h /dbg_interface/tags/rel_15/rtl/verilog/
44 Signal names changed to lower case. mohor 8151d 10h /dbg_interface/tags/rel_15/rtl/verilog/
43 Intentional error removed. mohor 8156d 10h /dbg_interface/tags/rel_15/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8156d 12h /dbg_interface/tags/rel_15/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8164d 09h /dbg_interface/tags/rel_15/rtl/verilog/

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