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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 94

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Rev Log message Author Age Path
94 temp version. Resets will be changed in next version. mohor 7482d 15h /dbg_interface/tags/rel_15/rtl/verilog/
93 tmp version. mohor 7483d 16h /dbg_interface/tags/rel_15/rtl/verilog/
92 temp version. mohor 7486d 19h /dbg_interface/tags/rel_15/rtl/verilog/
91 tmp version. mohor 7487d 14h /dbg_interface/tags/rel_15/rtl/verilog/
90 tmp version. mohor 7488d 09h /dbg_interface/tags/rel_15/rtl/verilog/
89 temp4 version. mohor 7489d 15h /dbg_interface/tags/rel_15/rtl/verilog/
88 temp3 version. mohor 7490d 10h /dbg_interface/tags/rel_15/rtl/verilog/
87 tmp2 version. mohor 7491d 15h /dbg_interface/tags/rel_15/rtl/verilog/
86 Tmp version. mohor 7504d 11h /dbg_interface/tags/rel_15/rtl/verilog/
83 Small fix. mohor 7504d 12h /dbg_interface/tags/rel_15/rtl/verilog/
82 New directory structure. New version of the debug interface. mohor 7504d 12h /dbg_interface/tags/rel_15/rtl/verilog/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7504d 12h /dbg_interface/tags/rel_15/rtl/verilog/
77 MBIST chain connection fixed. mohor 7565d 09h /dbg_interface/tags/rel_15/rtl/verilog/
73 CRC logic changed. mohor 7565d 11h /dbg_interface/tags/rel_15/rtl/verilog/
71 Mbist support added. simons 7567d 17h /dbg_interface/tags/rel_15/rtl/verilog/
67 Lower two address lines must be always zero. simons 7600d 13h /dbg_interface/tags/rel_15/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7601d 12h /dbg_interface/tags/rel_15/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7621d 13h /dbg_interface/tags/rel_15/rtl/verilog/
61 Lapsus fixed. simons 7649d 13h /dbg_interface/tags/rel_15/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7649d 13h /dbg_interface/tags/rel_15/rtl/verilog/

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