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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] - Rev 123

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Rev	Log message	Author	Age	Path
123	All flipflops are reset.	mohor	7460d 00h	/dbg_interface/tags/rel_19/
121	Port signals are all set to zero after reset.	mohor	7463d 00h	/dbg_interface/tags/rel_19/
120	test stall_test added.	mohor	7463d 03h	/dbg_interface/tags/rel_19/
119	cpu_stall_o activated as soon as bp occurs.	mohor	7463d 04h	/dbg_interface/tags/rel_19/
117	Define name changed.	mohor	7465d 00h	/dbg_interface/tags/rel_19/
116	Data latching changed when testing WB.	mohor	7465d 00h	/dbg_interface/tags/rel_19/
115	More debug data added.	mohor	7465d 04h	/dbg_interface/tags/rel_19/
114	CRC generation iand verification in bench changed.	mohor	7465d 05h	/dbg_interface/tags/rel_19/
113	IDCODE test improved.	mohor	7465d 06h	/dbg_interface/tags/rel_19/
112	dbg_tb_defines.v not used.	mohor	7466d 01h	/dbg_interface/tags/rel_19/
111	Define tap_defines.v added to test bench.	mohor	7466d 01h	/dbg_interface/tags/rel_19/
110	Waiting for "ready" improved.	mohor	7466d 02h	/dbg_interface/tags/rel_19/
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7466d 07h	/dbg_interface/tags/rel_19/
106	Sensitivity list updated.	simons	7467d 05h	/dbg_interface/tags/rel_19/
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7467d 20h	/dbg_interface/tags/rel_19/
102	New version.	mohor	7467d 20h	/dbg_interface/tags/rel_19/
101	Almost finished.	mohor	7467d 21h	/dbg_interface/tags/rel_19/
100	* empty log message *	mohor	7468d 23h	/dbg_interface/tags/rel_19/
99	cpu registers added.	mohor	7468d 23h	/dbg_interface/tags/rel_19/
97	Working.	mohor	7470d 02h	/dbg_interface/tags/rel_19/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] - Rev 123

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