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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] - Rev 19

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Rev	Log message	Author	Age	Path
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8263d 22h	/dbg_interface/tags/rel_19/
18	Reset signals are not combined any more.	mohor	8266d 07h	/dbg_interface/tags/rel_19/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8289d 21h	/dbg_interface/tags/rel_19/
16	bs_chain_o port added.	mohor	8291d 20h	/dbg_interface/tags/rel_19/
15	bs_chain_o added.	mohor	8291d 22h	/dbg_interface/tags/rel_19/
14	Document updated.	mohor	8292d 19h	/dbg_interface/tags/rel_19/
13	Signal names changed to lowercase.	mohor	8292d 22h	/dbg_interface/tags/rel_19/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8293d 22h	/dbg_interface/tags/rel_19/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8314d 18h	/dbg_interface/tags/rel_19/
10	First official release 1.0.	mohor	8318d 22h	/dbg_interface/tags/rel_19/
9	Working version. Few bugs fixed, comments added.	mohor	8318d 22h	/dbg_interface/tags/rel_19/
8	Asynchronous set/reset not used in trace any more.	mohor	8319d 20h	/dbg_interface/tags/rel_19/
7	First official release 1.0.	mohor	8319d 20h	/dbg_interface/tags/rel_19/
6	Minor changes for simulation.	mohor	8319d 20h	/dbg_interface/tags/rel_19/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8320d 18h	/dbg_interface/tags/rel_19/
4	Initial official release.	mohor	8325d 18h	/dbg_interface/tags/rel_19/
2	Initial official release.	mohor	8325d 18h	/dbg_interface/tags/rel_19/
1	Standard project directories initialized by cvs2svn.		8325d 18h	/dbg_interface/tags/rel_19/

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