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[/] [dbg_interface/] [tags/] [rel_19/] - Rev 31

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31 trst synchronization is not needed and was removed. mohor 8194d 03h /dbg_interface/tags/rel_19/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8205d 08h /dbg_interface/tags/rel_19/
29 Document revised and put tp better form. mohor 8208d 21h /dbg_interface/tags/rel_19/
28 TDO and TDO Enable signal are separated into two signals. mohor 8241d 05h /dbg_interface/tags/rel_19/
27 Warnings from synthesys tools fixed. mohor 8255d 06h /dbg_interface/tags/rel_19/
26 Warnings from synthesys tools fixed. mohor 8255d 06h /dbg_interface/tags/rel_19/
25 trst signal is synchronized to wb_clk_i. mohor 8256d 02h /dbg_interface/tags/rel_19/
24 CRC changed so more thorough testing is done. mohor 8257d 04h /dbg_interface/tags/rel_19/
23 Trace disabled by default. mohor 8263d 06h /dbg_interface/tags/rel_19/
22 Register length fixed. mohor 8263d 06h /dbg_interface/tags/rel_19/
21 CRC is returned when chain selection data is transmitted. mohor 8264d 02h /dbg_interface/tags/rel_19/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8265d 05h /dbg_interface/tags/rel_19/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8277d 06h /dbg_interface/tags/rel_19/
18 Reset signals are not combined any more. mohor 8279d 15h /dbg_interface/tags/rel_19/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8303d 04h /dbg_interface/tags/rel_19/
16 bs_chain_o port added. mohor 8305d 04h /dbg_interface/tags/rel_19/
15 bs_chain_o added. mohor 8305d 05h /dbg_interface/tags/rel_19/
14 Document updated. mohor 8306d 03h /dbg_interface/tags/rel_19/
13 Signal names changed to lowercase. mohor 8306d 06h /dbg_interface/tags/rel_19/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8307d 06h /dbg_interface/tags/rel_19/

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