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[/] [dbg_interface/] [tags/] [rel_19/] - Rev 84

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Rev Log message Author Age Path
84 Removed files that are not needed any more. mohor 7505d 07h /dbg_interface/tags/rel_19/
83 Small fix. mohor 7505d 07h /dbg_interface/tags/rel_19/
82 New directory structure. New version of the debug interface. mohor 7505d 07h /dbg_interface/tags/rel_19/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7505d 07h /dbg_interface/tags/rel_19/
80 New version of the debug interface. Not finished, yet. mohor 7505d 08h /dbg_interface/tags/rel_19/
77 MBIST chain connection fixed. mohor 7566d 04h /dbg_interface/tags/rel_19/
75 Simulation files. mohor 7566d 06h /dbg_interface/tags/rel_19/
74 Removed. mohor 7566d 06h /dbg_interface/tags/rel_19/
73 CRC logic changed. mohor 7566d 06h /dbg_interface/tags/rel_19/
71 Mbist support added. simons 7568d 13h /dbg_interface/tags/rel_19/
70 A pdf copy of existing doc document. simons 7575d 15h /dbg_interface/tags/rel_19/
69 WBCNTL added, multiple CPU support described. simons 7596d 04h /dbg_interface/tags/rel_19/
67 Lower two address lines must be always zero. simons 7601d 08h /dbg_interface/tags/rel_19/
65 WB_CNTL register added, some syncronization fixes. simons 7602d 08h /dbg_interface/tags/rel_19/
63 Three more chains added for cpu debug access. simons 7622d 09h /dbg_interface/tags/rel_19/
61 Lapsus fixed. simons 7650d 08h /dbg_interface/tags/rel_19/
59 Reset value for riscsel register set to 1. simons 7650d 09h /dbg_interface/tags/rel_19/
57 Multiple cpu support added. simons 7650d 10h /dbg_interface/tags/rel_19/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7917d 06h /dbg_interface/tags/rel_19/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7917d 07h /dbg_interface/tags/rel_19/

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