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[/] [dbg_interface/] [tags/] [rel_19/] - Rev 90

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Rev Log message Author Age Path
90 tmp version. mohor 7476d 21h /dbg_interface/tags/rel_19/
89 temp4 version. mohor 7478d 03h /dbg_interface/tags/rel_19/
88 temp3 version. mohor 7478d 21h /dbg_interface/tags/rel_19/
87 tmp2 version. mohor 7480d 02h /dbg_interface/tags/rel_19/
86 Tmp version. mohor 7492d 22h /dbg_interface/tags/rel_19/
85 New directory structure. New debug interface. mohor 7492d 23h /dbg_interface/tags/rel_19/
84 Removed files that are not needed any more. mohor 7492d 23h /dbg_interface/tags/rel_19/
83 Small fix. mohor 7492d 23h /dbg_interface/tags/rel_19/
82 New directory structure. New version of the debug interface. mohor 7492d 23h /dbg_interface/tags/rel_19/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7492d 23h /dbg_interface/tags/rel_19/
80 New version of the debug interface. Not finished, yet. mohor 7493d 00h /dbg_interface/tags/rel_19/
77 MBIST chain connection fixed. mohor 7553d 20h /dbg_interface/tags/rel_19/
75 Simulation files. mohor 7553d 22h /dbg_interface/tags/rel_19/
74 Removed. mohor 7553d 22h /dbg_interface/tags/rel_19/
73 CRC logic changed. mohor 7553d 22h /dbg_interface/tags/rel_19/
71 Mbist support added. simons 7556d 05h /dbg_interface/tags/rel_19/
70 A pdf copy of existing doc document. simons 7563d 07h /dbg_interface/tags/rel_19/
69 WBCNTL added, multiple CPU support described. simons 7583d 20h /dbg_interface/tags/rel_19/
67 Lower two address lines must be always zero. simons 7589d 01h /dbg_interface/tags/rel_19/
65 WB_CNTL register added, some syncronization fixes. simons 7590d 00h /dbg_interface/tags/rel_19/

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