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[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 80

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Rev Log message Author Age Path
80 New version of the debug interface. Not finished, yet. mohor 7491d 14h /dbg_interface/tags/rel_19/bench/
75 Simulation files. mohor 7552d 12h /dbg_interface/tags/rel_19/bench/
73 CRC logic changed. mohor 7552d 12h /dbg_interface/tags/rel_19/bench/
63 Three more chains added for cpu debug access. simons 7608d 14h /dbg_interface/tags/rel_19/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8086d 13h /dbg_interface/tags/rel_19/bench/
38 Few outputs for boundary scan chain added. mohor 8142d 14h /dbg_interface/tags/rel_19/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8146d 13h /dbg_interface/tags/rel_19/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8286d 16h /dbg_interface/tags/rel_19/bench/
15 bs_chain_o added. mohor 8288d 17h /dbg_interface/tags/rel_19/bench/
13 Signal names changed to lowercase. mohor 8289d 18h /dbg_interface/tags/rel_19/bench/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8290d 18h /dbg_interface/tags/rel_19/bench/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8311d 14h /dbg_interface/tags/rel_19/bench/
9 Working version. Few bugs fixed, comments added. mohor 8315d 18h /dbg_interface/tags/rel_19/bench/
6 Minor changes for simulation. mohor 8316d 16h /dbg_interface/tags/rel_19/bench/
5 Trace fixed. Some registers changed, trace simplified. mohor 8317d 14h /dbg_interface/tags/rel_19/bench/
2 Initial official release. mohor 8322d 14h /dbg_interface/tags/rel_19/bench/

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